? semiconductor components industries, llc, 2006 march, 2006 ? rev. 2 1 publication order number: NTMFS4709N/d NTMFS4709N power mosfet 30 v, 94 a, single n ? channel, soic ? 8 fl features ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? these are pb ? free devices applications ? vcore applications ? dc ? dc converters ? low side switching maximum ratings (t j =25 c unless otherwise stated) rating symbol value unit drain ? to ? source voltage v dss 30 v gate ? to ? source voltage v gs 20 v continuous drain current r ja (note 1) steady state t a = 25 c i d 18 a t a = 85 c 13 power dissipation r ja (note 1) t a = 25 c p d 2.35 w continuous drain current r ja (note 2) t a = 25 c i d 11 a t a = 85 c 8.0 power dissipation r ja (note 2) t a = 25 c p d 0.91 w continuous drain current r jc (note 1) t c = 25 c i d 94 a t c = 85 c 68 power dissipation r jc (note 1) t c = 25 c p d 62.5 w pulsed drain cur- rent t a = 25 c, t p = 10 s i dm 140 a current limited by package t a = 25 c i dmaxpkg 140 a operating junction and storage temperature t j , t stg ? 55 to +150 c source current (body diode) i s 62.5 a drain to source dv/dt 10 v/ns single pulse drain ? to ? source avalanche energy t j = 25 c, v dd = 50 v, v gs = 10 v, i l = 30 a pk , l = 1.0 mh, r g = 25 e as 450 mj lead temperature for soldering purposes (1/8? from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surface ? mounted on fr4 board using 1 sq ? in pad, 1 oz cu. 2. surface ? mounted on fr4 board using the minimum recommended pad size. http://onsemi.com device package shipping ? ordering information NTMFS4709Nt1g soic ? 8 fl (pb ? free) 1500 / tape & reel soic ? 8 flat lead case 488aa style 1 marking diagram & pin assignment 1 4709n = specific device code a = assembly location y = year ww = work week = pb ? free package 4709n ayww s n ? channel d s g 30 v 4.0 m @ 4.5 v 2.85 m @ 10 v r ds(on) typ 94 a i d max v (br)dss s s g d d d d NTMFS4709Nt3g 5000 / tape & reel soic ? 8 fl (pb ? free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. (note: microdot may be in either location)
NTMFS4709N http://onsemi.com 2 thermal resistance maximum ratings rating symbol value unit junction ? to ? case (drain) r jc 2.0 c/w junction ? to ? ambient ? steady state (note 3) r ja 53.2 junction ? to ? ambient ? steady state (note 4) r ja 137.8 3. surface ? mounted on fr4 board using 1 sq in pad, 1 oz cu. 4. surface ? mounted on fr4 board using the minimum recommended pad size. electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 5.6 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1.0 a t j = 125 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , id = 250 a 1.0 3.0 v negative threshold temperature coefficient v gs(th) /t j 5.6 mv/ c drain ? to ? source on resistance r ds(on) v gs = 11.5 v i d = 30 a 2.8 m i d = 15 a 2.8 v gs = 10 v i d = 30 a 2.85 3.6 v gs = 4.5 v i d = 30 a 4.0 5.5 i d = 15 a 4.0 forward transconductance g fs v ds = 15 v, i d = 15 a 41 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = 12 v 2370 pf output capacitance c oss 1240 reverse transfer capacitance c rss 305 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v; i d = 30 a 20 nc threshold gate charge q g(th) 2.4 gate ? to ? source charge q gs 4.5 gate ? to ? drain charge q gd 11 total gate charge q g(tot) v gs = 11.5 v, v ds = 15 v; i d = 30 a 48 nc threshold gate charge q g(th) 4.0 gate ? to ? source charge q gs 6.5 gate ? to ? drain charge q gd 10.6 switching characteristics (note 6) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 15 v, i d = 30 a, r g = 3.0 16 ns rise time t r 173 turn ? off delay time t d(off) 20 fall time t f 105 5. pulse test: pulse width 300 s, duty cycle 2% 6. switching characteristics are independent of operating junction temperatures.
NTMFS4709N http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise specified) parameter unit max typ min test condition symbol switching characteristics (note 6) turn ? on delay time t d(on) v gs = 11.5 v, v ds = 15 v, i d = 30 a, r g = 3.0 8.5 ns rise time t r 87 turn ? off delay time t d(off) 31.5 fall time t f 8.5 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 20 a t j = 25 c 0.75 1.0 v v gs = 0 v, i s = 50 a t j = 25 c 0.85 v gs = 0 v, i s = 20 a t j = 125 c 0.7 reverse recovery time t rr v gs = 0 v, d is /d t = 100 a/ s, i s = 25 a 48 ns charge time t a 23 discharge time t b 25 reverse recovery charge q rr 55 nc package parasitic values gate resistance r g t a = 25 c 0.65 5. pulse test: pulse width 300 s, duty cycle 2% 6. switching characteristics are independent of operating junction temperatures.
NTMFS4709N http://onsemi.com 4 0 10 20 30 40 50 60 0246810 v gs = 3 v 2.6 v 2.2 v t j = 25 c i d , drain current (a) v ds , drain ? to ? source voltage (v) 3.5 v 4.5 v 10 v figure 1. on ? region characteristics t j = 125 c t j = ? 55 c t j = 25 c i d , drain current (a) v gs , gate ? to ? source voltage (v) figure 2. transfer characteristics v ds 10 v 0 0.001 0.002 0.003 0.004 0 102030405060 r ds(on) , drain ? to ? source resistance ( ) i d , drain current (a) figure 3. on ? resistance versus drain current and temperature t = 125 c t = ? 55 c t = 25 c v gs = 11.5 v 0 0.001 0.002 0.003 0.004 10 20 30 40 50 60 figure 4. on ? resistance versus drain current and gate voltage v gs = 4.5 v v gs = 11.5 v t j = 25 c r ds(on) , drain ? to ? source resistance ( ) i d , drain current (a) 0 0.5 1 1.5 2 ? 50 ? 25 0 25 50 75 100 125 150 r ds(on) , drain ? to ? source resistance (normalized) t j , temperature ( c) figure 5. on ? resistance variation with temperature i d = 30 a v gs = 10 v 100 1000 10000 100000 0 5 10 15 20 25 30 v gs = 0 v t j = 125 c t j = 150 c i dss , leakage (na) v ds , drain ? to ? source voltage (v) figure 6. drain ? to ? source leakage current versus voltage 0.005 0.006 t = 150 c 0.005 0 0 10 20 30 40 50 60 012345
NTMFS4709N http://onsemi.com 5 0 1000 2000 3000 4000 10 5 0 5 10152025 v gs = 0 v v gs , gate ? to ? source voltage (v) gate ? to ? source or drain ? to ? source voltage (v) figure 7. capacitance variation c, capacitance (pf) v ds = 0 v c iss c iss c oss c rss c rss t j = 25 c v gs v ds 0 2 4 6 8 10 0 1020304050 q g , total gate charge (nc) figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge q t q gd q gs i d = 30 a t j = 25 c 1 10 100 1 10 100 t, time (ns) t r t d(on) t d(off) t f r g , gate resistance ( ) figure 9. resistive switching time variation versus gate resistance v dd = 15 v i d = 30 a v gs = 11.5 v 0 10 20 30 0.2 0.4 1 v sd , source ? to ? drain voltage (v) figure 10. diode forward voltage versus current i s , source current (a) v gs = 0 v t j = 25 c 0 100 200 300 400 500 600 700 25 50 75 100 125 150 eas, single pulse drain ? to ? source avalanche energy (mj) t j , starting junction temperature ( c) figure 11. maximum avalanche energy versus starting junction temperature i d = 36 a 12 1000 0.6 0.8 0
NTMFS4709N http://onsemi.com 6 package dimensions m 3.00 3.40 0 ??? 3.80 12 dfn6 5*6*1 1.27 pitch (so8 fl) case 488aa ? 01 issue b notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. 1234 5 6 top view side view bottom view d1 e1 d e 2 2 b a 0.20 c 0.20 c 2 x 2 x dim min nom millimeters a 0.90 0.99 a1 0.00 ??? b 0.33 0.41 c 0.23 0.28 d 5.15 bsc d1 4.50 4.90 d2 3.50 ??? e 6.15 bsc e1 5.50 5.80 e2 3.45 ??? e 1.27 bsc g 0.51 0.61 k 0.51 ??? l 0.51 0.61 l1 0.05 0.17 a 0.10 c 0.10 c detail a 14 6 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l detail a a1 e 3 x c 4 x c seating plane 5 max 1.20 0.05 0.51 0.33 5.10 4.22 6.10 4.30 0.71 ??? 0.71 0.20 style 1: pin 1. source 2. source 3. source 4. gate 5. drain 6. drain m *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.270 2x 0.750 1.000 0.905 0.475 4.530 1.530 4.560 0.495 3.200 1.330 0.965 2x 2x 3x 4x 4x
NTMFS4709N http://onsemi.com 7 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?t ypicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license un der its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended f or surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in a ny manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NTMFS4709N/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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